SH7712 Datasheet, PDF (316/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.2.9 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Channels A and B are used in two independent channel conditions or under the sequential
condition.
2. A break is set before or after instruction execution.
3. Specify whether to include the number of execution times on channel B in comparison
conditions.
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
6. Enable ASID check.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Bit
31 to 22
21
20
Initial
Bit Name Value R/W

All 0 R
BASMA 0
R/W
BASMB 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Break ASID Mask A
Specifies whether bits in channel A break ASID7 to
ASID0 (BASA7 to BASA0) which are set in BASRA are
masked or not.
0: All BASRA bits are included in the break conditions
and the ASID is checked
1: All BASRA bits are not included in the break
conditions and the ASID is not checked
Break ASID Mask B
Specifies whether bits in channel B break ASID7 to
ASID0 (BASB7 to BASB0) which are set in BASRB are
masked or not.
0: All BASRB bits are included in the break conditions
and the ASID is checked
1: All BASRB bits are not included in the break conditions
and the ASID is not checked
Rev. 1.00 Dec. 27, 2005 Page 274 of 932
REJ09B0269-0100