SH7712 Datasheet, PDF (304/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.5.2 Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT or INTEVT2.
The code in INTEVT or INTEVT2 can be used as an offset for branching to the specific
handler.
2. Clear the interrupt source in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing the BL bit in step 4. See figure 8.3 on a sample interrupt
operation flowchart.
Rev. 1.00 Dec. 27, 2005 Page 262 of 932
REJ09B0269-0100