SH7712 Datasheet, PDF (910/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
24.3.3 AC Bus Timing
Table 24.7 Bus Timing (1)
(Conditions: V Q = V Q-RTC = 3.0 to 3.6 V, V = V -PLL1 = V -PLL2 = 1.4 to 1.6 V,
CC
CC
CC
CC
CC
V_SSQ = V_SS = V_SSQ-RTC = V_SS-PLL1 = V_SS-PLL2 = 0 V, T_a = –20 to 75°C, clock mode 0/1/2/4/5/6/7)
66.67 MHz
Item
Symbol Min.
Max.
Unit Figure
Address delay time 1
t
1
AD1
Address delay time 2
t
—
AD2
Address setup time
t
0
AS
Address hold time
t_AH
0
BS delay time
t_BSD
—
CS delay time 1
t_CSD1
1
Read/write delay time 1 t
1
RWD1
Read strobe delay time t
—
RSD
12
ns
1/2 t +12
cyc
—
—
10
10
10
1/2 t +10
cyc
24.17 to 24.42
24.21
24.17 to 24.20
24.17 to 24.35, 24.39 to
24.42
24.17 to 24.42
24.17 to 24.21, 24.39 to
24.40
Read data setup time 1 t
RDS1
1/2 t +6 —
cyc
24.17 to 24.20, 24.39 to
24.42
Read data setup time 2 t_RDS2
6
—
24.22 to 24.25, 24.30 to
24.32
Read data setup time 3 t_RDS3
Read data hold time 1
t_RDH1
1/2 t_cyc+6 —
0
—
24.21
24.17 to 24.20, 24.39 to
24.42
Read data hold time 2 t
2
—
RDH2
24.22 to 24.25, 24.30 to
24.32
Read data hold time 3 t
0
RDH3
Write enable delay time t
—
WED
—
1/2 t +10
cyc
24.21
24.17 to 24.21, 24.39 to
24.40
Write data delay time 1 t_WDD1
—
12
24.17 to 24.20, 24.39 to
24.42
Write data delay time 2 t_WDD2
—
12
24.26 to 24.29, 24.33 to
24.35
Write data hold time 1 t
1
—
WDH1
Write data hold time 2 t
1
—
WDH2
24.17 to 24.20
24.26 to 24.29, 24.33 to
24.35
Rev. 1.00 Dec. 27, 2005 Page 868 of 932
REJ09B0269-0100