SH7712 Datasheet, PDF (199/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
4.1.2 Exception Event Register (EXPEVT)
EXPEVT is assigned to address H′FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified by the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Bit
Bit Name Initial Value R/W Description
31 to 12 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 EXPEVT *
R/W 12-bit Exception Code
Note: * Initialized to H′000 at power-on reset and H′020 at manual reset.
4.1.3 Interrupt Event Register (INTEVT)
INTEVT is assigned to address H′FFFFFFD8 and consists of the exception code or the interrupt
priority code. Whether the occurrence of an interrupt sets the exception code or the interrupt
priority code depends on the interrupt sources. (See section 8.3.5, Interrupt Exception Handling
and Priority, for details.) These exception codes and interrupt priority codes are automatically
specified by the hardware when an exception occurs. Only bits 11 to 0 in INTEVT can be re-
written using the software.
Bit
Bit Name
31 to 12 
11 to 0 INTEVT
Initial Value R/W
All 0
R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Rev. 1.00 Dec. 27, 2005 Page 157 of 932
REJ09B0269-0100