SH7712 Datasheet, PDF (36/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 24.59 MII Transmit Timing (Normal Operation)............................................................ 909
Figure 24.60 MII Transmit Timing (Case of Conflict)............................................................... 909
Figure 24.61 MII Receive Timing (Normal Operation) ............................................................. 910
Figure 24.62 MII Receive Timing (Case of Error) ..................................................................... 910
Figure 24.63 MDIO Input Timing .............................................................................................. 910
Figure 24.64 MDIO Output Timing ........................................................................................... 910
Figure 24.65 WOL Output Timing ............................................................................................. 911
Figure 24.66 EXOUT Output Timing......................................................................................... 911
Figure 24.67 CAMSEN Input Timing ........................................................................................ 911
Figure 24.68 ARBUBY Output Timing ..................................................................................... 911
Figure 24.69 I/O Port Timing ..................................................................................................... 912
Figure 24.70 TCK Input Timing................................................................................................. 913
Figure 24.71 TRST Input Timing (Reset Hold).......................................................................... 914
Figure 24.72 H-UDI Data Transfer Timing................................................................................ 914
Figure 24.73 ASEMD0 Input Timing......................................................................................... 914
Figure 24.74 ASEBRKAK Delay Time ..................................................................................... 914
Figure 24.75 Output Load Circuit .............................................................................................. 915
Figure 24.76 Load Capacitance vs. Delay Time......................................................................... 916
Appendix
Figure B.1 Package Dimensions (HQFP2828-256 (FP-256G/GV))........................................... 926
Figure B.2 Package Dimensions (P-LFBGA1717-256 (BP-256H/HV)) .................................... 927
Rev. 1.00 Dec. 27, 2005 Page xxxvi of xlii