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| SH7712 Datasheet, PDF (916/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 24 Electrical Characteristics
24.3.5 Burst ROM Timing
CKIO
A25 to A0
BS
CSn
RD/WR
T1
Tw
Twx
T2B
Twb
T2B
tAD1
tAD2
tAD2
tBSD
tBSD
tCSD1
tRWD1
tCSD1
tRWD1
tRSD
RD
D31 to D0
tRDS3
tRDH3*1
tRSD
tRDS3
tRDH3*1
WEn
tWED
DACKn*2
WAIT
tDACD
tWTH
tWTS
tWTH
tWTS
Notes: 1. tRDH3 is specified by earlier one of change of A25 to A0 or the RD rising edge.
2. DACKn is a waveform when active-low is specified.
tWED
tDACD
Figure 24.21 Burst ROM Read Cycle (One Access Wait, One External Wait,
One Burst Wait, Two Bursts)
Rev. 1.00 Dec. 27, 2005 Page 874 of 932
REJ09B0269-0100
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