SH7712 Datasheet, PDF (719/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Initial
Bit
Bit Name Value R/W
16
RINTM10 0
R/W
15 to 12 
All 0
R
11
TINTM41 0
R/W
10
TINTM31 0
R/W
9
TINTM21 0
R/W
8
TINTM11 0
R/W
7
OVFM1 0
R/W
6
RBSYM1 0
R/W
5

0
R
4
RINTM51 0
R/W
Section 18 Ethernet Controller (EtherC)
Description
MAC-0 CRC Error Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
MAC-1 Carrier Not Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
MAC-1 Carrier Lost Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
MAC-1 Collision Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
MAC-1 Transmission Time Out Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
Port 1 to 0 TSU FIFO Overflow Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
MAC-1 Overflow Alert Signal Output Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
MAC-1 Residual Bit Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
Rev. 1.00 Dec. 27, 2005 Page 677 of 932
REJ09B0269-0100