SH7712 Datasheet, PDF (104/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.10 Branch Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles
BF
label
10001011dddddddd
If T = 0, disp × 2 + PC → PC; 
3/1*
if T = 1, nop
BF/S
label
10001111dddddddd
Delayed branch,

2/1*
if T = 0, disp × 2 + PC → PC;
if T = 1, nop
BT
label
10001001dddddddd
If T = 1, disp × 2 + PC → PC; 
3/1*
if T = 0, nop
BT/S
label
10001101dddddddd
Delayed branch,

2/1*
if T = 1, disp × 2 + PC → PC;
if T = 0, nop
BRA
label
1010dddddddddddd
Delayed branch, disp × 2 + PC 
2
→ PC
BRAF Rm
0000mmmm00100011 Delayed branch,Rm + PC → PC 
2
BSR
label
1011dddddddddddd
Delayed branch, PC → PR, disp 
2
× 2 + PC → PC
BSRF Rm
0000mmmm00000011 Delayed branch, PC → PR, Rm 
2
+ PC → PC
JMP
@Rm 0100mmmm00101011 Delayed branch, Rm → PC

2
JSR
@Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm 
2
→ PC
RTS
0000000000001011
Delayed branch, PR → PC

2
Note: * One state when the branch is not executed.
T Bit











Rev. 1.00 Dec. 27, 2005 Page 62 of 932
REJ09B0269-0100