SH7712 Datasheet, PDF (306/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
• Maximum repeat times for the break condition (only for channel B): 2¹² – 1 times.
• Eight pairs of branch source/destination buffers.
Rev. 1.00 Dec. 27, 2005 Page 264 of 932
REJ09B0269-0100