SH7712 Datasheet, PDF (906/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
Stable input clock
EXTAL input,
CKIO input
PLL synchronization
PLL output,
CKIO output
Internal clock
IRL3 to IRL0/IRQ5 to IRQ0 interrupt request
Stable input clock
t_IRLSTB
t_PLL1
PLL synchronization
STATUS 0
STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from
EXTAL pin or CKIO pin in oscillation continuous mode.
Figure 24.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts
Multiplication ratio modified
EXTAL input^*1
(CKIO input)
CKIO output^*2
(PLL output)
Internal clock
t_PLL2
Notes: 1. CKIO input in clock mode 7
2. PLL output except in clock mode 7
Figure 24.11 PLL Synchronization Settling Time when Frequency Multiplication
Ratio Modified
Rev. 1.00 Dec. 27, 2005 Page 864 of 932
REJ09B0269-0100