SH7712 Datasheet, PDF (410/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Bit
5 to 2
Initial
Bit Name Value R/W

All 0 R
1
HW1
0
R/W
0
HW0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation. These bits
can be specified only in area 4.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
SDRAM*:
• CS2WCR
Bit
31 to
11
Initial
Bit Name Value R/W

All 0 R
10

1
R
9

0
R
8
A2CL1 1
R/W
7
A2CL0 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
CAS Latency for Area 2
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Rev. 1.00 Dec. 27, 2005 Page 368 of 932
REJ09B0269-0100