SH7712 Datasheet, PDF (170/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
result is aligned to the LSB of the destination, but the fixed-point multiply operation result is
aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always 0.
Multiply is always unconditional, but does not affect any condition code bits, DC, N, Z, V, and
GT , in DSR.
• Overflow Protection
The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0))
operation is executed as signed fixed-point multiply. The result is H'00 8000 0000 but it
does not mean (+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF
FFFF.
3.5.8 Shift Operations
Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations of arithmetic and logical shifts. Table 3.27 shows the variation of this type of operation.
The correspondence between each operand and registers, except for immediate operands, is the
same as the ALU fixed-point operations as shown in table 3.21.
Table 3.27 Variation of Shift Operations
Mnemonic
Function
PSHA Sx, Sy, Dz Arithmetic shift
PSHL Sx, Sy, Dz Logical shift
PSHA #Imm1, Dz Arithmetic shift with
immediate.
PSHL #Imm2, Dz Logical shift with
immediate.
Source 1
Sx
Sx
Dz
Source 2
Sy
Sy
Imm1
Destination
Dz
Dz
Dz
Dz
Imm2
Dz
–32 <= Imm1 <= +32, –16 <= Imm2 <= +16
Rev. 1.00 Dec. 27, 2005 Page 128 of 1044
REJ09B0269-0100