SH7712 Datasheet, PDF (818/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.4 Usage Notes
19.4.1 Using of EDTRR and EDRRR
[Problems]
While the Ethernet functions are being used, the TR bit in EDTRR or the RR bit in EDRRR is
cleared to 0 to stop the E-DAMC functions if the descriptor valid bit is invalid. When the request
bit (TR or RR) is cleared by the E-DMAC and the request bit (TR or RR) is set by the user's
firmware simultaneously, transmission or reception may not be started even if the request bit (TR
or RR) is set to 1.
[Occurring Condition]
When the user's firmware tries to set the request bit (TR or RR), while the request bit (TR or RR)
is 1.
[Avoiding Methods]
To prevent the simultaneous occurrence of the request bit (TR or RR) being cleared by the E-
DMAC and the request bit (TR or RR) being set by the user's firmware, the user's firmware should
set the request bit (TR or RR) after confirming that it is cleared by the E-DMAC.
The methods to clear the RR bit with E-DMAC are as follows.
(1) Confirmation of the TR bit
As a direct method, it is possible to confirm by reading the TR bit in EDTRR as 0.
As an indirect method, it is possible to confirm by reading the TDE bit in EESR as 1.
(2) Confirmation of the RR bit
As a direct method, it is possible to confirm by reading the RR bit in EDRRR as 0.
As an indirect method, it is possible to confirm by reading the RDE bit in EESR as 0.
Rev. 1.00 Dec. 27, 2005 Page 776 of 932
REJ09B0269-0100