GXLV Datasheet, PDF (99/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.1.2 Control Registers
The control registers for the GXLV processor use 32 KB of
the memory map, starting at GX_BASE+8000h (see Fig-
ure 4-2). This area is divided into internal bus interface
unit, graphics pipeline, display controller, memory control-
ler, and power management sections:
• The internal bus interface unit maps 100h locations
starting at GX_BASE+8000h.
• The graphics pipeline maps 200h locations starting at
GX_BASE+8100h.
• The display controller maps 100h locations starting at
GX_BASE+8300h.
• The memory controller maps 100h locations starting at
GX_BASE+8400h
• GX_BASE+8500h-8FFFh is dedicated to power
management registers for the serial packet transmis-
sion control, the user-defined power management
address space, Suspend Refresh, and SMI status for
Suspend/Resume.
The register descriptions are contained in the individual
subsections of this chapter. Accesses to undefined regis-
ters in the GXLV processor control register space will not
cause a hardware error.
4.1.3 Graphics Memory
Graphics memory is allocated from system DRAM by the
system BIOS. The GXLV processor’s graphics memory is
mapped into 4 MB starting at GX_BASE+800000h. This
area includes the frame buffer memory and storage for
internal display controller state. The size of the frame
buffer is a linear map whose size depends on the user’s
requirements (i.e., resolution, color depth, video buffer,
compression buffer, font caching, etc.). Frame buffer scan
lines are not contiguous in many resolutions, so software
that renders to the frame buffer must use a skip count to
advance between scan lines. The display controller can
use the graphics memory that lies between scan lines for
the compression buffer. Accessing graphics memory
between the end of a scan line and the start of another
can cause display problems. The skip count for all sup-
ported resolutions is shown in Table 4-2.
The graphics memory size is programmed by setting the
graphics memory base address in the memory controller
(see Table 4-15 on page 113). Display drivers communi-
cate with system BIOS about resolution changes, to
ensure that the correct amount of graphics memory is
allocated. Since no mechanism exists to recover system
DRAM from the operating system without rebooting when
a graphics resolution change requires an increased
amount of graphics memory, the system must be reboo-
ted!
.
Table 4-2. Display Resolution Skip Counts
Screen
Resolution
Pixel
Depth
Skip
Count
640x480
640x480
800x600
800x600
1024x768
1024x768
1280x1024
8 bits
16 bits
8 bits
16 bits
8 bits
16 bits
8 bits
1024
2048
1024
2048
1024
2048
2048
Revision 1.1
99
www.national.com