GXLV Datasheet, PDF (226/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Real Prot’d Real Prot’d
Mode Mode Mode Mode
Instruction
Opcode
INC Increment by 1
Register/Memory
F [111w] [mod 000 r/m]
Register (short form)
4 [0 reg]
INT Software Interrupt
INT i
CD #
Protected Mode:
-Interrupt or Trap to Same Privilege
-Interrupt or Trap to Different Privilege
-16-bit Task to 16-bit TSS by Task Gate
-16-bit Task to 32-bit TSS by Task Gate
-16-bit Task to V86 by Task Gate
-16-bit Task to 16-bit TSS by Task Gate
-32-bit Task to 32-bit TSS by Task Gate
-32-bit Task to V86 by Task Gate
-V86 to 16-bit TSS by Task Gate
-V86 to 32-bit TSS by Task Gate
-V86 to Privilege 0 by Trap Gate/Int Gate
INT 3
CC
INTO
CE
If OF==0
If OF==1 (INT 4)
INVD Invalidate Cache
0F 08
INVLPG Invalidate TLB Entry
0F 01 [mod 111 r/m]
IRET Interrupt Return
Real Mode
CF
Protected Mode:
-Within Task to Same Privilege
-Within Task to Different Privilege
-16-bit Task to 16-bit Task
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
JB/JNAE/JC Jump on Below/Not Above or Equal/Carry
8-bit Displacement
72 +
Full Displacement
0F 82 +++
JBE/JNA Jump on Below or Equal/Not Above
8-bit Displacement
76 +
Full Displacement
0F 86 +++
JCXZ/JECXZ Jump on CX/ECX Zero
E3 +
JE/JZ Jump on Equal/Zero
8-bit Displacement
74 +
Full Displacement
0F 84 +++
JL/JNGE Jump on Less/Not Greater or Equal
8-bit Displacement
7C +
Full Displacement
0F 8C +++
JLE/JNG Jump on Less or Equal/Not Greater
8-bit Displacement
7E +
Full Displacement
0F 8E +++
O D I T S Z A P C Clock Count
F F F F F F F F F (Reg/Cache Hit)
Issues
x- - - xxxx-
1
1
1
b
h
1
- - x0- - - - -
19
b,e g,j,k,r
33
55
184
190
124
187
193
127
187
193
64
INT
INT
4
4
INT
INT
---------
20
20
t
t
---------
15
15
x x x x x x x x x 13
20
39
169
175
109
172
178
112
g,h,j,k,r
---------
1
1
r
1
1
--------
1
1
r
1
1
---------
2
2
r
--------
1
1
r
1
1
--------
1
1
r
1
1
--------
1
1
r
1
1
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