GXLV Datasheet, PDF (224/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Real Prot’d Real Prot’d
Mode Mode Mode Mode
Instruction
Opcode
CALL Subroutine Call
Direct Within Segment
E8 +++
Register/Memory Indirect Within Segment
FF [mod 010 r/m]
Direct Intersegment
-Call Gate to Same Privilege
-Call Gate to Different Privilege No Par’s
-Call Gate to Different Privilege m Par’s
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
9A [unsigned full offset,
selector]
Indirect Intersegment
-Call Gate to Same Privilege
-Call Gate to Different Privilege No Par’s
-Call Gate to Different Privilege m Par’s
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
FF [mod 011 r/m]
CBW Convert Byte to Word
98
CDQ Convert Doubleword to Quadword
99
CLC Clear Carry Flag
F8
CLD Clear Direction Flag
FC
CLI Clear Interrupt Flag
FA
CLTS Clear Task Switched Flag
0F 06
CMC Complement the Carry Flag
F5
CMOVA/CMOVNBE Move if Above/Not Below or Equal
Register, Register/Memory
0F 47 [mod reg r/m]
CMOVBE/CMOVNA Move if Below or Equal/Not Above
Register, Register/Memory
0F 46 [mod reg r/m]
CMOVAE/CMOVNB/CMOVNC Move if Above or Equal/Not Below/Not Carry
Register, Register/Memory
0F 43 [mod reg r/m]
CMOVB/CMOVC/CMOVNAE Move if Below/Carry/Not Above or Equal
Register, Register/Memory
0F 42 [mod reg r/m]
CMOVE/CMOVZ Move if Equal/Zero
Register, Register/Memory
0F 44 [mod reg r/m]
CMOVNE/CMOVNZ Move if Not Equal/Not Zero
Register, Register/Memory
0F 45 [mod reg r/m]
CMOVG/CMOVNLE Move if Greater/Not Less or Equal
Register, Register/Memory
0F 4F [mod reg r/m]
CMOVLE/CMOVNG Move if Less or Equal/Not Greater
Register, Register/Memory
0F 4E [mod reg r/m]
CMOVL/CMOVNGE Move if Less/Not Greater or Equal
Register, Register/Memory
0F 4C [mod reg r/m]
CMOVGE/CMOVNL Move if Greater or Equal/Not Less
Register, Register/Memory
0F 4D [mod reg r/m]
CMOVO Move if Overflow
Register, Register/Memory
0F 40 [mod reg r/m]
CMOVNO Move if No Overflow
Register, Register/Memory
0F 41 [mod reg r/m]
CMOVP/CMOVPE Move if Parity/Parity Even
Register, Register/Memory
0F 4A [mod reg r/m]
CMOVNP/CMOVPO Move if Not Parity/Parity Odd
Register, Register/Memory
0F 4B [mod reg r/m]
O D I T S Z A P C Clock Count
F F F F F F F F F (Reg/Cache Hit)
Issues
---------
---------
---------
--------0
- 0- - - - - - -
- - 0- - - - - -
---------
--------x
3
3
b
3/4
3/4
9
14
24
45
51+2m
183
189
123
186
192
126
11
15
25
46
52+2m
184
190
124
187
193
127
3
3
2
2
1
1
4
4
6
6
7
7
c
3
3
h,j,k,r
m
l
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
---------
1
1
r
www.national.com
224
Revision 1.1