GXLV Datasheet, PDF (234/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
8.4 FPU INSTRUCTION SET
The processor core is functionally divided into the FPU,
and the integer unit. The FPU processes floating point
instructions only and does so in parallel with the integer
unit.
For example, when the integer unit detects a floating point
instruction without memory operands, after two clock
cycles the instruction passes to the FPU for execution.
The integer unit continues to execute instructions while
the FPU executes the floating point instruction. If another
FPU instruction is encountered, the second FPU instruc-
tion is placed in the FPU queue. Up to four FPU instruc-
tions can be queued. In the event of an FPU exception,
while other FPU instructions are queued, the state of the
CPU is saved to ensure recovery.
The FPU instruction set is summarized in Table 8-29. The
table uses abbreviations that are described Table 8-28.
Table 8-28. FPU Instruction Set Table Legend
Abbr.
n
TOS
ST(1)
ST(n)
M.WI
M.SI
M.LI
M.SR
M.DR
M.XR
M.BCD
CC
Env Regs
Description
Stack register number.
Top of stack register pointed to by SSS in the
status register.
FPU register next to TOS.
A specific FPU register, relative to TOS.
16-bit integer operand from memory.
32-bit integer operand from memory.
64-bit integer operand from memory.
32-bit real operand from memory.
64-bit real operand from memory.
80-bit real operand from memory.
18-digit BCD integer operand from memory.
FPU condition code.
Status, Mode Control and Tag Registers,
Instruction Pointer and Operand Pointer.
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