GXLV Datasheet, PDF (129/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.4.6 Graphics Pipeline Register Descriptions
The graphics pipeline maps 200h locations starting at
GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-
ters” on page 99 for instructions on accessing these regis-
ters. Table 4-23 summarizes the graphics pipeline
registers and Table 4-24 gives detailed register/bit for-
mats.
Table 4-23. Graphics Pipeline Configuration Register Summary
GX_BASE+
Memory Offset
Type Name / Function
Default Value
8100h-8103h
R/W GP_DST/START_Y/XCOOR
00000000h
Destination/Starting Y and X Coordinates Register: In BLT mode this register
specifies the destination Y and X positions for a BLT operation. In Vector mode it
specifies the starting Y and X positions in a vector.
8104-8107h
R/W GP_WIDTH/HEIGHT and GP_VECTOR_LENGTH/INIT_ERROR
00000000h
Width/Height or Vector Length/Initial Error Register: In BLT mode this register
specifies the BLT width and height in pixels. In Vector mode it specifies the vector
initial error and pixel length.
8108h-810Bh
R/W GP_SRC_X/YCOOR and GP_AXIAL/DIAG_ERROR
00000000h
Source X/Y Coordinate Axial/Diagonal Error Register: In BLT mode this register
specifies the BLT X and Y source. In Vector mode it specifies the axial and diago-
nal error for rendering a vector.
810Ch-810Fh
R/W GP_SRC_COLOR_0 and GP_SRC_COLOR_1
00000000h
Source Color Register: Determines the colors used when expanding mono-
chrome source data in either the 8-bpp mode or the 16-bpp mode.
8110h-8113h
R/W GP_PAT_COLOR_0 and GP_PAT_COLOR_1
00000000h
Graphics Pipeline Pattern Color Registers 0 and1: These two registers determine
the colors used when expanding pattern data.
8114h-8117h
R/W GP_PAT_COLOR_2 and GP_PAT_COLOR_3
00000000h
Graphics Pipeline Pattern Color Registers 2 and 3: These two registers deter-
mine the colors used when expanding pattern data.
8120h-8123h
R/W GP_PAT_DATA 0 through 3
00000000h
8124h-8127h
8128h-812Bh
812Ch-812Fh
R/W Graphics Pipeline Pattern Data Registers 0 through 3: Together these registers
R/W ^{contain 128 bits of pattern data.}
R/W ^{GP_PAT_DATA_0 corresponds to bits [31:0] of the pattern data.}
GP_PAT_DATA_1 corresponds to bits [63:32] of the pattern data.
00000000h
00000000h
00000000h
GP_PAT_DATA_2 corresponds to bits [95:64] of the pattern data.
GP_PAT_DATA_3 corresponds to bits [127:96] of the pattern data.
8140h-8143h
(Note)
R/W GP_VGA_WRITE
Graphics Pipeline VGA Write Patch Control Register: Controls the VGA memory
write path in the graphics pipeline.
xxxxxxxxh
8144h-8147h
(Note)
R/W GP_VGA_READ
Graphics Pipeline VGA Read Patch Control Register: Controls the VGA memory
read path in the graphics pipeline.
00000000h
8200h-8203h
R/W GP_RASTER_MODE
00000000h
Graphics Pipeline Raster Mode Register: This register controls the manipulation
of the pixel data through the graphics pipeline. Refer to Section 4.4.5 “Raster
Operations” on page 128.
8204h-8207h
R/W GP_VECTOR_MODE
00000000h
Graphics Pipeline Vector Mode Register: Writing to this register initiates the ren-
dering of a vector.
8208h-820Bh
R/W GP_BLT_MODE
00000000h
Graphics Pipeline BLT Mode Register: Writing to this initiates a BLT operation.
Note: The registers at GX_BASE+8140, 8144h, 8210h, and 8214h are located in the area designated for the graphics pipeline but
are used for VGA emulation purposes. Refer to Table 4-39 on page 165 for these register’s bit formats.
Revision 1.1
129
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