GXLV Datasheet, PDF (235/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
Table 8-29. FPU Instruction Set Summary
FPU Instruction
Opcode
F2XM1 Function Evaluation 2^x-1
D9 F0
FABS Floating Absolute Value
D9 E1
FADD Floating Point Add
Top of Stack
DC [1100 0 n]
80-bit Register
D8 [1100 0 n]
64-bit Real
DC [mod 000 r/m]
32-bit Real
D8 [mod 000 r/m]
FADDP Floating Point Add, Pop
DE [1100 0 n]
FIADD Floating Point Integer Add
32-bit integer
DA [mod 000 r/m]
16-bit integer
DE [mod 000 r/m]
FCHS Floating Change Sign
D9 E0
FCLEX Clear Exceptions
(9B) DB E2
FNCLEX Clear Exceptions
DB E2
FCMOVB Floating Point Conditional Move if
Below
DA [1100 0 n]
FCMOVE Floating Point Conditional Move if
Equal
DA [1100 1 n]
FCMOVBE Floating Point Conditional Move if
Below or Equal
DA [1101 0 n]
FCMOVU Floating Point Conditional Move if
Unordered
DA [1101 1 n]
FCMOVNB Floating Point Conditional Move if
Not Below
DB [1100 0 n]
FCMOVNE Floating Point Conditional Move if
Not Equal
DB [1100 1 n]
FCMOVNBE Floating Point Conditional Move if
Not Below or Equal
DB [1101 0 n]
FCMOVNU Floating Point Conditional Move if
Not Unordered
DB [1101 1 n]
FCOM Floating Point Compare
80-bit Register
D8 [1101 0 n]
64-bit Real
DC [mod 010 r/m]
32-bit Real
D8 [mod 010 r/m]
FCOMP Floating Point Compare, Pop
80-bit Register
D8 [1101 1 n]
64-bit Real
DC [mod 011 r/m]
32-bit Real
D8 [mod 011 r/m]
FCOMPP Floating Point Compare, Pop
Two Stack Elements
DE D9
FCOMI Floating Point Compare Real and Set EFLAGS
80-bit Register
DB [1111 0 n]
FCOMIP Floating Point Compare Real and Set EFLAGS, Pop
80-bit Register
DF [1111 0 n]
FUCOMI Floating Point Unordered Compare Real and Set EFLAGS
80-bit Integer
DB [1110 1 n]
FUCOMIP Floating Point Unordered Compare Real and Set EFLAGS, Pop
80-bit Integer
DF [1110 1 n]
FICOM Floating Point Integer Compare
32-bit integer
DA [mod 010 r/m]
16-bit integer
DE [mod 010 r/m]
FICOMP Floating Point Integer Compare, Pop
32-bit integer
DA [mod 011 r/m]
16-bit integer
DE [mod 011 r/m
Operation
TOS <--- 2^TOS-1
TOS <--- | TOS |
ST(n) <--- ST(n) + TOS
TOS <--- TOS + ST(n)
TOS <--- TOS + M.DR
TOS <--- TOS + M.SR
ST(n) <--- ST(n) + TOS; then pop TOS
TOS <--- TOS + M.SI
TOS <--- TOS + M.WI
TOS <--- - TOS
Wait then Clear Exceptions
Clear Exceptions
If (CF=1) ST(0) <--- ST(n)
If (ZF=1) ST(0) <--- ST(n)
If (CF=1 or ZF=1) ST(0) <--- ST(n)
If (PF=1) ST(0) <--- ST(n)
If (CF=0) ST(0) <--- ST(n)
If (ZF=0) ST(0) <--- ST(n)
If (CF=0 and ZF=0) ST(0) <--- ST(n)
If (DF=0) ST(0) <--- ST(n)
CC set by TOS - ST(n)
CC set by TOS - M.DR
CC set by TOS - M.SR
CC set by TOS - ST(n); then pop TOS
CC set by TOS - M.DR; then pop TOS
CC set by TOS - M.SR; then pop TOS
CC set by TOS - ST(1); then pop TOS and
ST(1)
EFLAG set by TOS - ST(n)
EFLAG set by TOS - ST(n); then pop TOS
EFLAG set by TOS - ST(n)
EFLAG set by TOS - ST(n); then pop TOS
CC set by TOS - M.WI
CC set by TOS - M.SI
CC set by TOS - M.WI; then pop TOS
CC set by TOS - M.SI; then pop TOS
Clock
Count
92 - 108
2
Issue
2
2
4-9
4-9
4-9
4-9
8 - 14
8 - 14
2
5
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
9 - 10
9 - 10
9 - 10
9 - 10
9 - 10
9 - 10
Revision 1.1
235
www.national.com