GXLV Datasheet, PDF (31/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Signal Definitions (Continued)
2.2 SIGNAL DESCRIPTIONS
2.2.1 System Interface Signals
Signal Name
BGA SPGA
Pin No. Pin No.
SYSCLK
P26
V34
CLKMODE[2:0]
M1, L1, G3, R2,
M3
S1
RESET
J3
M2
INTR
B18
D24
IRQ13
C22
C31
Type
I
I
I
I
O
Description
System Clock
PCI clock is connected to SYSCLK. The internal clock of the
GXLV processor is generated by a proprietary patented fre-
quency synthesis circuit which multiplies the SYSCLK input up to
ten times. The SYSCLK to core clock multiplier is configured
using the CLKMODE[2:0] inputs.
The SYSCLK input is a fixed frequency which can only be
stopped or varied when the GXLV processor is in full 3V Sus-
pend. (See Section 5.1.4 “3 Volt Suspend” on page 177 for
details regarding this mode.)
Clock Mode
These signals are used to set the core clock multiplier. The PCI
clock "SYSCLK" is multiplied by the value set by CLKMODE[2:0]
to generate the GXLV processor’s core clock.
CLKMODE[2:0]:
000 = SYSCLK multiplied by 4 (Test mode only)
001 = SYSCLK multiplied by 10
010 = SYSCLK multiplied by 9
011 = SYSCLK multiplied by 5
100 = SYSCLK multiplied by 4
101 = SYSCLK multiplied by 6
110 = SYSCLK multiplied by 7
111 = SYSCLK multiplied by 8
Reset
RESET aborts all operations in progress and places the
GXLV processor into a reset state. RESET forces the CPU and
peripheral functions to begin executing at a known state. All data
in the on-chip cache is invalidated upon RESET.
RESET is an asynchronous input but must meet specified setup
and hold times to guarantee recognition at a particular clock
edge. This input is typically generated during the Power-On-
Reset sequence.
(Maskable) Interrupt Request
INTR is a level-sensitive input that causes the GXLV processor to
suspend execution of the current instruction stream and begin
execution of an interrupt service routine. The INTR input can be
masked through the EFlags Register IF bit. (See Table 3-4 on
page 46 for bit definitions.)
Interrupt Request Level 13
IRQ13 is asserted if an on-chip floating point error occurs.
When a floating point error occurs, the GXLV processor asserts
the IRQ13 pin. The floating point interrupt handler then performs
an OUT instruction to I/O address F0h or F1h. The GXLV proces-
sor accepts either of these cycles and clears the IRQ13 pin.
Refer to Section 3.4.1 “I/O Address Space” on page 63 for fur-
ther information on IN/OUT instructions.
Revision 1.1
31
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