GXLV Datasheet, PDF (39/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Signal Definitions (Continued)
2.2.5 Power, Ground, and No Connect Signals
Signal Name
BGA SPGA
Pin No. Pin No.
Type
VSS
VCC2
VCC3
NC
Refer
to
Table 2-3
(Total of
71)
Refer
to
Table 2-5
(Total of
50)
Refer
to
Table 2-3
(Total of
32)
Refer
to
Table 2-5
(Total of
32)
Refer
to
Table 2-3
(Total of
32)
Refer
to
Table 2-5
(Total of
18)
D26,
E24,
AC5
E37,
F36, Q5,
X2, Z2,
AM36
GND
PWR
PWR
Description
Ground Connection
2.2V, 2.5V, or 2.9V (Nominal) Core Power Connection
3.3V (Nominal) I/O Power Connection
No Connection
A line designated as NC must be left disconnected.
2.2.6 Internal Test and Measurement Signals
Signal Name
BGA SPGA
Pin No. Pin No.
Type
FLT#
AC2
AJ3
I
RW_CLK
AE6
AL11
O
TEST[3:0]
TCLK
B22,
D28,
O
A23,
B32,
B21,
D26,
C21
A33
J2
P4
I
(PU)
(PU)
TDI
D2
F4
I
(PU)
(PU)
TDO
F1
J1
O
Description
Float
Float forces the GXLV processor to float all outputs in the high-
impedance state and to enter a power-down state.
Raw Clock
This output is the GXLV processor clock. This debug signal can
be used to verify clock operation.
SDRAM Test Outputs
These outputs are used for internal debug only.
Test Clock
JTAG test clock.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
Test Data Input
JTAG serial test-data input.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
Test Data Output
JTAG serial test-data output.
Revision 1.1
39
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