GXLV Datasheet, PDF (218/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
8.2 CPUID INSTRUCTION
The CPUID instruction (opcode 0FA2) allows the software
to make processor inquiries as to the vendor, family,
model, stepping, features and also provides cache infor-
mation. The GXLV supports both the standard and
National Semiconductor extended CPUID levels.
The presence of the CPUID instruction is indicated by the
ability to change the value of the ID Flag, bit 21 in the
EFLAGS register.
The CPUID level allows the CPUID instruction to return
different information in the EAX, EBX, ECX, and EDX reg-
isters. The level is determined by the initialized value of
the EAX register before the instruction is executed. A
summary of the CPUID levels is shown in Table 8-16.
Table 8-16. CPUID Levels Summary
CPUID
Type
Initialized
EAX
Register
Returned Data in EAX, EBX,
ECX, EDX Registers
Standard
Standard
Standard
Extended
Extended
Extended
Extended
Extended
Extended
0000 0000h
0000 0001h
0000 0002h
8000 0000h
8000 0001h
8000 0002h
8000 0003h
8000 0004h
8000 0005h
Maximum standard levels, CPU
vendor string
Model, family, type and features
TLB and cache information
Maximum extended levels
Extended model, family, type and
features
CPU marketing name string
TLB and L1 cache description
8.2.1.1 CPUID Instruction with EAX = 0000 0000h
Standard function 0h (EAX = 0) of the CPUID instruction
returns the maximum standard CPUID levels as well as
the processor vendor string.
After the instruction is executed, the EAX register contains
the maximum standard CPUID levels supported. The
maximum standard CPUID level is the highest acceptable
value for the EAX register input. This does not include the
extended CPUID levels.
The EBX through EDX registers contain the vendor string
of the processor as shown in Table 8-17.
Table 8-17. CPUID Data Returned when EAX = 0
Register
(Note)
Returned Contents
Description
EAX
2
Maximum Standard
Level
EBX
69
72
(iryC)
7943 Vendor ID String 1
EDX
73
6E
(snlx)
4978 Vendor ID String 2
ECX
64
61
(daet)
6574 Vendor ID String 3
Note: The register column is intentionally out of order.
8.2.1 Standard CPUID Levels
The standard CPUID levels are part of the standard x86
instruction set.
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