GXLV Datasheet, PDF (47/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Processor Programming (Continued)
3.3.2 System Register Set
The System Register Set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level
programmers who generate operating systems and mem-
ory management programs. Associated with the System
Register Set are certain tables and segments which are
listed in Table 3-5.
The Control Registers control certain aspects of the
GXLV processor such as paging, coprocessor functions,
and segment protection.
The Configuration Registers are used to define the
GXLV CPU setup including cache management.
The Debug Registers provide debugging facilities for the
GXLV processor and enable the use of data access
breakpoints and code execution breakpoints.
The Test Registers provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB).
The Descriptor Table Register hold descriptors that
manage memory segments and tables, interrupts and
task switching. The tables are defined by corresponding
registers.
The two Task State Segment Tables defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.
The ID Registers allow BIOS and other software to iden-
tify the specific CPU and stepping.
System Management Mode (SMM) control information is
stored in the SMM Registers.
Table 3-5 lists the system register sets along with their
size and function.
Table 3-5. System Register Set
Group
Control
Registers
Name
CR0
CR2
CR3
Configuration
Registers
Debug
Registers
CR4
CCRn
DR0
DR1
DR2
DR3
Test
Registers
Descriptor
Tables
DR6
DR7
TR3
TR4
TR5
TR6
TR7
GDT
IDT
Descriptor
Table
Registers
Task State
Segment and
Registers
ID
Registers
SMM
Registers
Performance
Registers
LDT
GDTR
IDTR
LDTR
TSS
TR
DIRn
SMARn
SMHRn
PCR0
Function
System Control
Register
Page Fault Linear
Address Register
Page Directory Base
Register
Time Stamp Counter
Configuration Control
Registers
Linear Breakpoint
Address 0
Linear Breakpoint
Address 1
Linear Breakpoint
Address 2
Linear Breakpoint
Address 3
Breakpoint Status
Breakpoint Control
Cache Test
Cache Test
Cache Test
TLB Test Control
TLB Test Data
General Descriptor Table
Interrupt Descriptor
Table
Local Descriptor Table
GDT Register
IDT Register
LDT Register
Task State Segment
Table
TSS Register Setup
Device Identification
Registers
SMM Address Region
Registers
SMM Header Addresses
Performance Control
Register
Width
(Bits)
32
32
32
32
8
32
32
32
32
32
32
32
32
32
32
32
32
32
16
32
32
16
16
16
8
8
8
8
Revision 1.1
47
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