GXLV Datasheet, PDF (151/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
Table 4-31. Display Controller Timing Registers (Continued)
Bit
Name
Description
GX_BASE+833Ch-833Fh
C_FP_H_TIMING Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
RSVD
Reserved: Set to 0.
26:16
FP_H_SYNC
_END
Flat Panel Horizontal Sync End: The pixel count at which the flat panel horizontal sync signal
becomes inactive minus 1.
15:11
RSVD
Reserved: Set to 0.
10:0
FP_H_SYNC Flat Panel Horizontal Sync Start: The pixel count at which the flat panel horizontal sync signal
_START
becomes active minus 1.
Note: These values are specified in pixels rather than character clocks to allow precise control over sync position. For flat panels
which combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee that the
sync signal will meet proper setup and hold times.
GX_BASE+8340h-8343h
DC_V_TIMING_1 Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
RSVD
Reserved: Set to 0.
26:16
V_TOTAL
Vertical Total: The total number of lines for a given frame scan minus 1. The value is necessarily
greater than the V_ACTIVE field because it includes border lines and blanked lines. If the display is
interlaced, the total number of lines must be odd, so this value should be an even number.
15:11
RSVD
Reserved: Set to 0.
10:0
V_ACTIVE
Vertical Active: The total number of lines for the displayed portion of a frame scan minus 1. For flat
panels, if this value is less than the panel active vertical resolution (V_PANEL), the parameters
V_BLANK_START, V_BLANK_END, V_SYNC_START, and V_SYNC_END should be reduced by
the following value (V_ADJUST) to achieve vertical centering: V_ADJUST = (V_PANEL –
V_ACTIVE) / 2
If the display is interlaced, the number of active lines should be even, so this value should be an odd
number.
Note: These values are specified in lines.
GX_BASE+8344h-8347h
DC_V_TIMING_2 Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
RSVD
Reserved: Set to 0.
26:16
V_BLANK_END Vertical Blank End: The line at which the vertical blanking signal becomes inactive minus 1. If the
display is interlaced, no border is supported, so this value should be identical to V_TOTAL.
15:11
RSVD
Reserved: Set to 0.
10:0
V_BLANK_
Vertical Blank Start: The line at which the vertical blanking signal becomes active minus 1. If the
START
display is interlaced, this value should be programmed to V_ACTIVE plus 1.
Note: These values are specified in lines. For interlaced display, no border is supported, so blank timing is implied by the total/active
timing.
GX_BASE+8348h-834Bh
DC_V_TIMING_3 Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
RSVD
Reserved: Set to 0.
26:16
V_SYNC_END Vertical Sync End: The line at which the CRT vertical sync signal becomes inactive minus 1.
15:11
RSVD
Reserved: Set to 0.
10:0 V_SYNC_START Vertical Sync Start: The line at which the CRT vertical sync signal becomes active minus 1. For
interlaced display, note that the vertical counter is incremented twice during each line and since
there are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for one
field and at the end of a line for the subsequent field.
Note: These values are specified in lines.
GX_BASE+834Ch-834Fh
DC_FP_V_TIMING Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
RSVD
Reserved: Set to 0.
26:16
FP_V_SYNC
_END
Flat Panel Vertical Sync End: The line at which the flat panel vertical sync signal becomes inactive
minus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal sync
prior to being output to the panel.
15:11
RSVD
Reserved: Set to 0.
10:0
FP_VSYNC Flat Panel Vertical Sync Start: The line at which the internal flat panel vertical sync signal
_START
becomes active minus 2. Note that the internal flat panel vertical sync is latched by the flat panel
horizontal sync prior to being output to the panel.
Note: These values are specified in lines.
Revision 1.1
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