GXLV Datasheet, PDF (178/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Power Management (Continued)
5.2 SUSPEND MODES AND BUS CYCLES
The following subsections describe the bus cycles of the
various suspend states.
5.2.1 Timing Diagram for Suspend-on-Halt
The CPU enters Suspend-on-Halt as a result of executing
a halt (HLT) instruction if the SUSP_HALT bit in CCR2
(Index C2h[3]) is set. When the HLT instruction is exe-
cuted, the halt PCI cycle is run on the PCI bus normally
and then the SUSPA# pin will go active to indicate that the
processor has entered the suspend state. This state is
slightly is different from CPU Suspend because of how
Suspend-on-Halt is entered and how it is exited. Suspend-
on-Halt is exited upon recognition of an unmasked INTR
or an SMI#. Normally SUSPA# is deactivated within six
SYSCLKS from the detection of an active interrupt. How-
ever, the deactivation of SUSPA# may be delayed until the
end of an active refresh cycle.
The CPU allows PCI master accesses during a HALT-initi-
ated Suspend mode. The SUSPA# pin will go inactive dur-
ing the duration of the PCI activity. If the CPU is in the
middle of a PCI master access when the Halt instruction is
executed, the assertion of SUSPA# will be delayed until
the PCI access is completed. See Figure 5-1 for timing
details.
PCI HALT CYCLE
SYSCLK
FRAME#
C/BE[3:0]#
I
O
X
AD[15:0]
X
I
X
IRDY#
INTR, SMI#
SUSPA#
Figure 5-1. HALT-Initiated Suspend Mode
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