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GXLV Datasheet, PDF (133/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions | |||
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Integrated Functions (Continued)
Table 4-24. Graphics Pipeline Configuration Registers (Continued)
Bit
Name Description
1
PB (RO) Pipeline Busy (Read Only): Indicates that the graphics pipeline is processing data.
The âPipeline Busyâ bit differs from the âBLT Busyâ bit in that the former only indicates that the graphics pipe-
line is processing data. The âBLT Busyâ bit also indicates that the memory controller has not yet processed
all of the requests for the current operation.
The âPipeline Busyâ bit must be clear before loading a BLT buffer if the previous BLT operation used the
same BLT buffer.
0
BB (RO) BLT Busy (Read Only): Indicates that a BLT / vector operation is in progress.
The âBLT Busyâ bit must be clear before accessing the frame buffer directly.
GX_BASE+8210h-8213h
GP_VGA_BASE (R/W)
Default Value = xxxxxxxxh
Note that the registers at GX_BASE+8210h is located in the area designated for the graphics pipeline but is used for VGA emulation
purposes. Refer to Table 4-39 on page 165 for this registerâs bit formats.
GX_BASE+8214h-8217h
GP_VGA_LATCH Register (R/W)
Default Value = xxxxxxxxh
Note that the registers at GX_BASE+8214h is located in the area designated for the graphics pipeline but is used for VGA emulation
purposes. Refer to Table 4-39 on page 165 for this registerâs bit formats.
Revision 1.1
133
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