GXLV Datasheet, PDF (51/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Processor Programming (Continued)
Table 3-10. Configuration Register Map
Register
(Index)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Registers
CCR1 (C1h)
CCR2 (C2h)
CCR3 (C3h)
CCR4 (E8h)
CCR7 (EBh)
PCR (20h)
USE_SUSP
LSS_34
RSVD
RSVD
LSS_23
LSS_12
CPUID
LSSER
SMI_NEST
FPU_FAST_
EN
RSVD
WT1
MAPEN
DTE_EN
SUSP_HLT
SUSP_SMM
_EN
MEM_BYP
SMAC
LOCK_NW
RSVD
IORT2
NMI
RSVD
SMM Base Header Address Registers
SMHR0 (B0h)
A7
A6
A5
A4
A3
A2
SMHR1 (B1h)
A15
A14
A13
A12
A11
A10
SMHR2 (B2h)
A23
A22
A21
A20
A19
A18
SMHR3 (B3h)
A31
A30
A29
A28
A27
A26
SMAR0 (CDh)
A31
A30
A29
A28
A27
A26
SMAR1 (CEh)
A23
A22
A21
A20
A19
A18
SMAR2 (CFh)
A15
A14
A13
A12
SIZE3
SIZE2
Device ID Registers
DIR0 (FEh)
DIR1 (FFh)
DID3
SID3
DID2
SID2
DID1
SID1
DID0
SID0
MULT3
RID3
MULT2
RID2
Graphics/VGA Related Registers
GCR (B8h)
VGACTL (B9h)
VGAM0 (BAh)
VGAM1 (BBh)
VGAM2 (BCh)
VGAM3 (BDh)
RSVD
RSVD
Scratchpad Size
Enable SMI
for VGA
memory
B8000h to
BFFFFh
VGA Mask Register Bits [7:0]
VGA Mask Register Bits [15:8]
VGA Mask Register Bits [23:16]
VGA Mask Register Bits [31:24]
USE_SMI
RSVD
RSVD
NMI_EN SMI_LOCK
IORT1
IORT0
RSVD
EMMX
A1
A9
A17
A26
A25
A17
SIZE1
A0
A8
A16
A24
A24
A16
SIZE0
MULT1
RID1
MULT0
RID0
Base Address Code
Enable SMI
for VGA
memory
B0000h to
B7FFFh
Enable SMI
for VGA
memory
A0000h to
AFFFFh
Revision 1.1
51
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