GXLV Datasheet, PDF (41/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

3.0 Processor Programming
This section describes the internal operations of the
Geode GXLV processor from a programmer’s point of
view. It includes a description of the traditional “core” pro-
cessing and FPU operations. The integrated function reg-
isters are described at the end of this chapter.
The primary register sets within the processor core
include:
• Application Register Set
• System Register Set
• Model Specific Register Set
The initialization of the major registers within the core are
shown in Table 3-1.
The integrated function sets are located in main memory
space and include:
• Internal Bus Interface Unit Register Set
• Graphics Pipeline Register Set
• Display Controller Register Set
• Memory Controller Register Set
• Power Management Register Set
3.1 CORE PROCESSOR INITIALIZATION
The GXLV processor is initialized when the RESET signal
is asserted. The processor is placed in real mode and the
registers listed in Table 3-1 are set to their initialized val-
ues. RESET invalidates and disables the CPU cache, and
turns off paging. When RESET is asserted, the CPU ter-
minates all local bus activity and all internal execution.
While RESET is asserted the internal pipeline is flushed
and no instruction execution or bus activity occurs.
Approximately 150 to 250 external clock cycles after
RESET is deasserted, the processor begins executing
instructions at the top of physical memory (address loca-
tion FFFFFFF0h). The actual number of clock cycles
depends on the clock scaling in use. Also, before execu-
tion begins, an additional 2²⁰ clock cycles are needed
when self-test is requested.
Typically, an intersegment jump is placed at FFFFFFF0h.
This instruction will force the processor to begin execution
in the lowest 1 MB of address space.
Table 3-1 lists the core registers and illustrates how they
are initialized.
Table 3-1. Initialized Core Register Controls
Register
Register Name
Initialized Contents
Comments
EAX
EBX
ECX
EDX
EBP
ESI
EDI
ESP
EFLAGS
EIP
ES
CS
SS
DS
FS
GS
IDTR
GDTR
LDTR
TR
CR0
CR2
CR3
CR4
CCR1
CCR2
CCR3
CCR4
CCR7
Accumulator
xxxxxxxxh
Base
xxxxxxxxh
Count
xxxxxxxxh
Data
xxxx 04 [DIR0]h
Base Pointer
xxxxxxxxh
Source Index
xxxxxxxxh
Destination Index
xxxxxxxxh
Stack Pointer
xxxxxxxxh
Flags
00000002h
Instruction Pointer
0000FFF0h
Extra Segment
0000h
Code Segment
F000h
Stack Segment
0000h
Data Segment
0000h
Extra Segment
0000h
Extra Segment
0000h
Interrupt Descriptor Table Register Base = 0, Limit = 3FFh
Global Descriptor Table Register xxxxxxxxh
Local Descriptor Table Register xxxxh
Task Register
xxxxh
Control Register 0
60000010h
Control Register 2
xxxxxxxxh
Control Register 3
xxxxxxxxh
Control Register 4
00000000h
Configuration Control 1
00h
Configuration Control 2
00h
Configuration Control 3
00h
Configuration Control 4
00h
Configuration Control 7
00h
0000 0000h indicates self-test passed.
DIR0 = Device ID
See Table 3-4 on page 46 for bit definitions.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to FFFF0000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
See Table 3-7 on page 49 for bit definitions.
See Table 3-7 on page 49 for bit definitions.
See Table 3-7 on page 48 for bit definitions.
See Table 3-7 on page 48 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
Revision 1.1
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