GXLV Datasheet, PDF (109/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.3.2 Memory Organizations
The memory controller supports JEDEC standard syn-
chronous DRAMs in 16 Mbit and 64 Mbit configurations.
Supported configurations are shown in Table 4-11. Note
that when using x4 SDRAM, there are 16 devices per
bank. The GXLV supports a total of 32 devices. There are
only two banks total when x4 devices are used.
Depth
1
2
4
8
16
32
64
Table 4-11. Synchronous DRAM Configurations
Organization
Row
Address
Column
Address
Bank
Address
1 Mx16
2 Mx8
2 Mx32
2 Mx32
2 Mx32
2 Mx32
4 Mx4
4 Mx16
4 Mx16
4 Mx16
8 Mx8
8 Mx8
8 Mx32
8 Mx32
16 Mx4
16 Mx4
16 Mx16
16 Mx16
32 Mx8
64 Mx4
A10-A0
A10-A0
A10-A0
A10-A0
A11-A0
A12-A0
A10-A0
A11-A0
A12-A0
A10-A0
A11-A0
A12-A0
A11-A0
A12-A0
A11-A0
A12-A0
A12-A0
A11-A0
A12-A0
A12-A0
A7-A0
A8-A0
A7-A0
A8-A0
A6-A0
A6-A0
A9-A0
A7-A0
A7-A0
A9-A0
A8-A0
A8-A0
A8-A0
A7-A0
A9-A0
A9-A0
A8-A0
A9-A0
A9-A0
A9-A0,A11
BA0
BA0
BA1-BA0
BA0
BA1-BA0
BA0
BA0
BA1-BA0
BA0
BA0
BA1-BA0
BA0
BA1-BA0
BA1-BA0
BA1-BA0
BA0
BA1-BA0
BA1-BA0
BA1-BA0
BA1-BA0
Total # of
Address bits
20
21
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
25
26
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