GXLV Datasheet, PDF (223/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
Table 8-27. Processor Core Instruction Set Summary
Flags
Real Prot’d Real Prot’d
Mode Mode Mode Mode
Instruction
AAA ASCII Adjust AL after Add
AAD ASCII Adjust AX before Divide
AAM ASCII Adjust AX after Multiply
AAS ASCII Adjust AL after Subtract
ADC Add with Carry
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
ADD Integer Add
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
AND Boolean AND
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
ARPL Adjust Requested Privilege Level
From Register/Memory
BB0_Reset Set BLT Buffer 0 Pointer to the Base
BB1_Reset Set BLT Buffer 1 Pointer to the Base
BOUND Check Array Boundaries
If Out of Range (Int 5)
If In Range
BSF Scan Bit Forward
Register, Register/Memory
BSR Scan Bit Reverse
Register, Register/Memory
BSWAP Byte Swap
BT Test Bit
Register/Memory, Immediate
Register/Memory, Register
BTC Test Bit and Complement
Register/Memory, Immediate
Register/Memory, Register
BTR Test Bit and Reset
Register/Memory, Immediate
Register/Memory, Register
BTS Test Bit and Set
Register/Memory
Register (short form)
37
D5 0A
D4 0A
3F
Opcode
1 [00dw] [11 reg r/m]
1 [000w] [mod reg r/m]
1 [001w] [mod reg r/m]
8 [00sw] [mod 010 r/m]###
1 [010w] ###
0 [00dw] [11 reg r/m]
0 [000w] [mod reg r/m]
0 [001w] [mod reg r/m]
8 [00sw] [mod 000 r/m]###
0 [010w] ###
2 [00dw] [11 reg r/m]
2 [000w] [mod reg r/m]
2 [001w] [mod reg r/m]
8 [00sw] [mod 100 r/m]###
2 [010w] ###
63 [mod reg r/m]
0F 3A
0F 3B
62 [mod reg r/m]
0F BC [mod reg r/m]
0F BD [mod reg r/m]
0F C[1 reg]
0F BA [mod 100 r/m]#
0F A3 [mod reg r/m]
0F BA [mod 111 r/m]#
0F BB [mod reg r/m]
0F BA [mod 110 r/m]#
0F B3 [mod reg r/m
0F BA [mod 101 r/m]
0F AB [mod reg r/m]
O D I T S Z A P C Clock Count
F F F F F F F F F (Reg/Cache Hit)
u -- -uux ux
3
3
u- - - xxuxu
7
7
u - - - x x u x u 19
19
u- - - uuxux
3
3
Issues
x- - - xxxxx
1
1
1
1
1
1
b
h
1
1
1
1
x- - - xxxxx
1
1
1
1
1
1
b
h
1
1
1
1
0- - - xxux0
1
1
1
1
1
1
b
h
1
1
1
1
- - - - - x- - -
2
2
9
a
h
2
2
---------
8+INT 8+INT
7
7
b, e g,h,j,k,r
- - - - - x - - - 4/9+n 4/9+n b
h
- - - - - x - - - 4/11+n 4/11+n b
h
---------
6
6
--------x
1
1
b
h
1/7
1/7
--------x
2
2
b
h
2/8
2/8
--------x
2
2
b
h
2/8
2/8
--------x
2
2
b
h
2/8
2/8
Revision 1.1
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