GXLV Datasheet, PDF (104/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.2.5 Internal Bus Interface Unit Registers
The Internal Bus Interface Unit maps 100h bytes starting
at GX_BASE+8000h. However only 16 bytes (four 32-bit
registers) are defined. Refer to Section 4.1.2 “Control
Registers” on page 99 for instructions on accessing these
registers.
Table 4-8 summarizes the four 32-bit registers contained
in the Internal Bus Interface Unit and Table 4-9 gives the
register/bit formats.
GX_BASE+
Memory Offset
8000h-8003h
8004h-8007h
8008h-800Bh
800Ch-800Fh
Table 4-8. Internal Bus Interface Unit Register Summary
Type
R/W
R/W
R/W
R/W
Name/Function
BC_DRAM_TOP
Top of DRAM — Contains the highest available address of system memory not
including the memory that is set aside for graphics memory, which corresponds to
1 GB of memory. The largest possible value for the register is 3FFFFFFFh.
BC_XMAP_1
Memory X-Bus Map Register 1 (A and B Region Control) — Contains the region
control of the A and B regions and the SMI controls required for VGA emulation.
PCI access to internal registers and the A20M function are also controlled by this
register.
BC_XMAP_2
Memory X-Bus Map Register 2 (C and D Region Control) — Contains region con-
trol fields for eight regions in the address range C0h through DCh.
BC_XMAP_3
Memory X-Bus Map Register 3 (E and F Region Control) — Contains the region
control fields for memory regions in the address range E0h through FCh.
Default
Value
3FFFFFFFh
00000000h
00000000h
00000000h
Table 4-9. Internal Bus Interface Unit Registers
Bit
Name
Description
GX_BASE+8000h-8003h
31:28
27:17
RSVD
TOP OF
DRAM
16:0
RSVD
GX_BASE+8004h-8007h
31:29
28
RSVD
GEB8
27:24
23
22
21
20
B8
RSVD
PRAE
A20M
GEB0
19:16
15
B0
SMID
BC_DRAM_TOP Register (R/W)
Default Value = 3FFFFFFFh
Reserved: Set to 0.
Top of DRAM:
000h = Minimum top or 0001FFFFh (128 KB)
7FFh = Maximum top or 0FFFFFFFh (256 MB)
Reserved: Set to 1.
BC_XMAP_1 Register (R/W)
Default Value = 00000000h
Reserved: Set to 0.
Graphics Enable for B8 Region: Allow memory R/W operations for address range B8000h to BFFFFh
be directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEB8 region is always non-
cacheable. In the region control field (B8) the cache enable bit (bit 2) is ignored.
(Used for VGA emulation.)
B8 Region: Region control field for address range B8000h to BFFFFh.
Note: Refer to Table 4-10 on page 106 for decode.
Reserved: Set to 0.
PCI Register Access Enable: Allow PCI Slave to access internal registers on the X-Bus:
0 = Disable; 1 = Enable.
Address Bit 20 Mask: Address bit 20 is always forced to a zero except for SMI accesses:
0 = Disable; 1 = Enable.
Graphics Enable for B0 Region: Allow memory R/W operations for address range B8000h to BFFFFh
be directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEB0 region is always non-
cacheable. In the region control field (B0) the cache enable bit (bit 2) is ignored.
(Used for VGA emulation.)
B0 Region: Region control field for address range B0000h to B7FFFh.
Note: Refer to Table 4-10 on page 106 for decode.
SMID: All I/O accesses for address range 3D0h to 3DFh generate an SMI: 0 = Disable; 1 = Enable.
(Used for VGA virtualization.)
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