GXLV Datasheet, PDF (90/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Processor Programming (Continued)
3.7.8.2 CPU States Related to SMM and Suspend
Mode
The state diagram shown in Figure 3-12 illustrates the var-
ious CPU states associated with SMM and Suspend
mode. While in the SMM service routine, the GXLV pro-
cessor core can enter Suspend mode either by (1) execut-
ing a halt (HLT) instruction or (2) by asserting the SUSP#
input.
During SMM operations and while in SUSP#-initiated
Suspend mode, an occurrence of either NMI or INTR is
latched. (In order for INTR to be latched, the IF flag,
EFLAGS register bit 9, must be set.) The INTR or NMI is
serviced after exiting Suspend mode.
If Suspend mode is entered through a HLT instruction
from the operating system or application software, the
reception of an SMI# interrupt causes the CPU to exit
Suspend mode and enter SMM. If Suspend mode is
entered through the hardware (SUSP# = 0) while the
operating system or application software is active, the
CPU latches one occurrence of INTR, NMI, and SMI#.
Suspend Mode
(SUSPA# = 0)
NMI or INTR
Interrupt Service
Routine
HLT*
IRET*
NMI or INTR
RESET
SMI# = 0
OS/Application
Software
SMI# = 0
SMINT*
RSM*
SUSP# = 0
SUSP# = 1
Suspend Mode
(SUSPA# = 0)
(INTR, NMI and SMI# latched)
Non-SMM Operations
SMM Operations
SMM Service Routine
(SMI# = 0)
NMI or INTR
IRET*
Interrupt Service
Routine
*Instructions
SUSP# = 0
SUSP# = 1
Suspend Mode
(SUSPA# = 0)
(INTR and NMI latched)
IRET*
HLT*
Suspend Mode
(SUSPA# = 0)
NMI or INTR
Interrupt Service
Routine
Figure 3-12. SMM and Suspend Mode State Diagram
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