GXLV Datasheet, PDF (63/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Processor Programming (Continued)
3.4 ADDRESS SPACES
The GXLV processor can directly address either memory
or I/O space. Figure 3-2 illustrates the range of addresses
available for memory address space and I/O address
space. For the CPU, the addresses for physical memory
range between 0000 0000h and FFFFFFFFh (4 GB).
The accessible I/O address space ranges between
00000000h and 0000FFFFh (64 KB). The CPU does not
use coprocessor communication space in upper I/O space
between 800000F8h and 8000 00FFh as do the 386-style
CPUs. The I/O locations 22h and 23h are used for GXLV
processor configuration register access.
3.4.1 I/O Address Space
The CPU I/O address space is accessed using IN and
OUT instructions to addresses referred to as “ports.” The
accessible I/O address space is 64 KB and can be
accessed as 8-, 16- or 32-bit ports.
The GXLV processor configuration registers reside within
the I/O address space at port addresses 22h and 23h and
are accessed using the standard IN and OUT instructions.
The configuration registers are modified by writing the
index of the configuration register to Port 22h, and then
transferring the data through Port 23h. Accesses to the
on-chip configuration registers do not generate external
I/O cycles. However, each operation on Port 23h must be
preceded by a write to Port 22h with a valid index value.
Otherwise, subsequent Port 23h operations will communi-
cate through the I/O port to produce external I/O cycles with-
out modifying the on-chip configuration registers. Write
operations to port 22h outside of the CPU index range
(C0h-CFh and FEh-FFh) result in external I/O cycles and
do not affect the on-chip configuration registers. Reading
Port 22h generates external I/O cycles.
I/O accesses to port address range 3B0h through 3DFh
can be trapped to SMI by the CPU if this option is enabled
in the BC_XMAP_1 register (see SMIB, SMIC, and SMID
bits in Table 4-9 on page 104). Figure 3-2 illustrates the
I/O address space.
FFFFFFFFh
Physical
Memory Space
FFFFFFFFh
Accessible
Programmed
I/O Space
Physical Memory
4 GB
Not
Accessible
00000000h
0000FFFFh
00000000h
64 KB
Figure 3-2. Memory and I/O Address Spaces
CPU General
Configuration
Register I/O
Space
00000023h
00000022h
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