GXLV Datasheet, PDF (123/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.3.7 SDRAM Interface Clocking
The GXLV processor drives the SDCLK to the SDRAMs;
one for each DIMM bank. All the control, data, and
address signals driven by the memory controller are sam-
pled by the SDRAM at the rising edge of SDCLK. SDCLK-
OUT is a reference signal used to generate SDCLKIN.
Read data is sampled by the memory controller at the ris-
ing edge of SDCLKIN.
The delay for SDCLKIN from SDCLKOUT must be
designed so that it lags the SDCLKs at the DRAM by
approximately 1 ns (check application notes for additional
information). The delay should also include the SDCLK
transmission line delay. All four SDCLK traces on the
board should be the same length, so there is no skew
between them. These guidelines allow the memory inter-
face to operate at a higher performance.
SDCLK[3:0]
SDCLKOUT
Geode™ GXLV
Processor
SDCLKIN
SDCLK0
SDCLK1
DIMM
0
Delay
SDCLK2
SDCLK3
DIMM
1
Figure 4-9. SDCLKIN Clocking
Revision 1.1
123
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