GXLV Datasheet, PDF (96/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

4.0 Integrated Functions
The integrated functions in the Geode GXLV processor
are:
• Internal bus interface
• SDRAM memory controller
• High-performance 2D graphics accelerator
• Display controller with separate CRT and TFT data
paths
• PCI bridge
The design organizes the memory controller, graphics
pipeline and display controller into a Unified Memory
Architecture (UMA). UMA simplifies system designs and
significantly reduces overall system costs associated with
high chip count, small footprint designs. Performance deg-
radation in traditional UMA systems is reduced through
the use of National Semiconductor’s Display Compression
Technology (DCT) architecture.
Figure 4-1 shows the major functional blocks of the GXLV
processor and how the Internal Bus Interface Unit oper-
ates as the interface between the processor’s core units
and the integrated functions.
This section details how the integrated functions and
Internal Bus Interface Unit operate and their respective
registers.
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
Internal Bus Interface Unit
X-Bus
FPU
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
SDRAM Port
CS5530
(CRT/LCD TFT)
Figure 4-1. Internal Block Diagram
PCI Bus
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