GXLV Datasheet, PDF (230/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Real Prot’d Real Prot’d
Mode Mode Mode Mode
Instruction
REP OUTS Output String
Opcode
F3 6[111w]
REP STOS Store String
F3 A[101w]
REPE CMPS Compare String
Find non-match
F3 A[011w]
REPE SCAS Scan String
Find non-AL/AX/EAX
F3 A[111w]
REPNE CMPS Compare String
Find match
F2 A[011w]
REPNE SCAS Scan String
Find AL/AX/EAX
F2 A[111w]
RET Return from Subroutine
Within Segment
C3
Within Segment Adding Immediate to SP
C2 ##
Intersegment
CB
Intersegment Adding Immediate to SP
CA ##
Protected Mode: Different Privilege Level
-Intersegment
-Intersegment Adding Immediate to SP
ROL Rotate Left
Register/Memory by 1
D[000w] [mod 000 r/m]
Register/Memory by CL
D[001w] [mod 000 r/m]
Register/Memory by Immediate
C[000w] [mod 000 r/m] #
ROR Rotate Right
Register/Memory by 1
D[000w] [mod 001 r/m]
Register/Memory by CL
D[001w] [mod 001 r/m]
Register/Memory by Immediate
C[000w] [mod 001 r/m] #
RSDC Restore Segment Register and Descriptor 0F 79 [mod sreg3 r/m]
RSLDT Restore LDTR and Descriptor
0F 7B [mod 000 r/m]
RSTS Restore TSR and Descriptor
0F 7D [mod 000 r/m]
RSM Resume from SMM Mode
0F AA
SAHF Store AH in FLAGS
9E
SAL Shift Left Arithmetic
Register/Memory by 1
D[000w] [mod 100 r/m]
Register/Memory by CL
D[001w] [mod 100 r/m]
Register/Memory by Immediate
C[000w] [mod 100 r/m] #
SAR Shift Right Arithmetic
Register/Memory by 1
D[000w] [mod 111 r/m]
Register/Memory by CL
D[001w] [mod 111 r/m]
Register/Memory by Immediate
C[000w] [mod 111 r/m] #
SBB Integer Subtract with Borrow
Register to Register
1[10dw] [11 reg r/m]
Register to Memory
1[100w] [mod reg r/m]
Memory to Register
1[101w] [mod reg r/m]
Immediate to Register/Memory
8[00sw] [mod 011 r/m] ###
Immediate to Accumulator (short form)
1[110w] ###
SCAS Scan String
A [111w]
SETB/SETNAE/SETC Set Byte on Below/Not Above or Equal/Carry
To Register/Memory
0F 92 [mod 000 r/m]
SETBE/SETNA Set Byte on Below or Equal/Not Above
To Register/Memory
0F 96 [mod 000 r/m]
SETE/SETZ Set Byte on Equal/Zero
To Register/Memory
0F 94 [mod 000 r/m]
O D I T S Z A P C Clock Count
F F F F F F F F F (Reg/Cache Hit)
---------
---------
24+4n
9+2n
24+4n\
39+4n
9+2n
Issues
b
h,m
b
h
x - - - x x x x x 11+4n 11+4n b
h
x - - - x x x x x 9+3n 9+3n b
h
x - - - x x x x x 11+4n 11+4n b
h
x - - - x x x x x 9+3n 9+3n b
h
---------
3
3
b g,h,j,k,r
3
3
10
13
10
13
35
35
x- - - - - - - x
2
u- - - - - - - x
2
u- - - - - - - x
2
2
b
h
2
2
x- - - - - - - x
2
2
b
h
u- - - - - - - x
2
2
u- - - - - - - x
2
2
---------
11
11
s
s
---------
11
11
s
s
---------
11
11
s
s
x x x x x x x x x 57
57
s
s
- - - - xxxxx
1
1
x- - - xxux x
1
u- - - xxux x
2
u- - - xxux x
1
1
b
h
2
1
x- - - xxuxx
2
u- - - xxuxx
2
u- - - xxuxx
2
2
b
h
2
2
x- - - xxxxx
1
1
1
1
1
x- - - xxxxx
2
1
b
h
1
1
1
1
2
b
h
---------
1
1
h
---------
1
1
h
---------
1
1
h
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