GXLV Datasheet, PDF (214/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Instruction Set (Continued)
8.1.1 Prefix (Optional)
Prefix bytes can be placed in front of any instruction to
modify the operation of that instruction. When more than
one prefix is used, the order is not important. There are
five types of prefixes that can be used:
1. Segment Override explicitly specifies which segment
register the instruction will use for effective address
calculation.
2. Address Size switches between 16-bit and 32-bit
addressing by selecting the non-default address size.
3. Operand Size switches between 16-bit and 32-bit
operand size by selecting the non-default operand
size.
4. Repeat is used with a string instruction to cause the
instruction to be repeated for each element of the
string.
5. Lock is used to assert the hardware LOCK# signal
during execution of the instruction.
Table 8-3 lists the encoding for different types of prefix
bytes.
Table 8-3. Instruction Prefix Summary
Prefix
Encoding Description
ES:
CS:
SS:
DS:
FS:
GS:
Operand
Size
Address
Size
LOCK
REPNE
REP/REPE
26h
Override segment default, use ES
for memory operand.
2Eh
Override segment default, use CS
for memory operand.
36h
Override segment default, use SS
for memory operand.
3Eh
Override segment default, use DS
for memory operand.
64h
Override segment default, use FS
for memory operand.
65h
Override segment default, use GS
for memory operand.
66h
Make operand size attribute the
inverse of the default.
67h
Make address size attribute the
inverse of the default.
F0h
Assert LOCK# hardware signal.
F2h
Repeat the following string
instruction.
F3h
Repeat the following string
instruction.
8.1.2 Opcode
The opcode field specifies the operation to be performed
by the instruction. The opcode field is either one or two
bytes in length and may be further defined by additional
bits in the mod r/m byte. Some operations have more than
one opcode, each specifying a different form of the opera-
tion. Certain opcodes name instruction groups. For exam-
ple, opcode 80h names a group of operations that have
an immediate operand and a register or memory operand.
The reg field may appear in the second opcode byte or in
the mod r/m byte.
The opcode may contain w, d, s and eee opcode fields, for
example, as shown in Table 8-27 on page 223.
8.1.2.1 w Field (Operand Size)
When used, the 1-bit w field selects the operand size dur-
ing 16-bit and 32-bit data operations. See Table 8-4.
w
Field
0
1
Table 8-4. w Field Encoding
Operand Size
16-Bit Data
Operations
8 bits
16 bits
32-Bit Data
Operations
8 bits
32 bits
8.1.2.2 d Field (Operand Direction)
When used, the 1-bit d field determines which operand is
taken as the source operand and which operand is taken
as the destination. See Table 8-5.
Table 8-5. d Field Encoding
d
Field
Direction of
Operation
Source
Operand
Destination
Operand
0 Register-to-Register
reg
mod r/m
or
or
Register-to-Memory
mod ss-index-
base
1 Register-to-Register mod r/m
reg
or
or
Memory-to-Register mod ss-index-
base
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