GXLV Datasheet, PDF (107/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.3 MEMORY CONTROLLER
The memory controller arbitrates requests from the X-Bus
(processor and PCI), display controller, and graphics pipe-
line.
The GXLV processor supports LVTTL (low voltage TTL)
technology. LVTTL technology allows the SDRAM inter-
face of the memory controller to run at frequencies up to
100 MHz.
The SDRAM clock is a function of the core clock. The
SDRAM bus can be run at speeds that range between 66
MHz and 100 MHz. The core clock can be divided down
from 2 to 5 in half clock increments to generate the
SDRAM clock. SDRAM frequencies between 79 MHz and
100 MHz are only supported for certain types of closed
systems and strict design rules must be adhered to. For
further details, contact your local National Semiconductor
technical support representative.
A basic block diagram of the memory controller is shown
in Figure 4-3.
Processor/PCI
Control
Display Controller
Control
Graphics Pipeline
Control
Processor/PCI I/F
Display Controller I/F
Graphics Pipeline I/F
RFSH
Arbiter
SDRAM
Sequence
Controller
Timing
Controller
DQM[7:0]
RASA#,RASB#
CASA#,CASB#
CS[3:0]#
WEA#/WEB#
CKEA, CKEB
Processor/PCI Address
Display Controller Address
Graphics Pipeline Address
Processor/PCI Data
Configuration
Registers
Address
Control/MUX
Processor/PCI
Write Buffer (16 Bytes)
MA[12:0]
BA[1:0]
Display Controller Data
Graphics Pipeline Data
Core Clock (ph2)
Display Controller
Write Buffer (16 Bytes)
Graphics Controller
Write Buffer (16 Bytes)
Clock Divider
2, 2.5, 3, 3.5, 4, 4.5, 5
Read Buffer
(16 Bytes)
MD[63:0]
SDCLK[3:0]
Figure 4-3. Memory Controller Block Diagram
Revision 1.1
107
www.national.com