GXLV Datasheet, PDF (154/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.5.13 FIFO Diagnostic Registers
The FIFO Diagnostic Register group consists of two 32-bit
registers located at GX_BASE+8378h and
GX_BASE+837Ch. These registers are summarized in
Table 4-28 on page 141, and Table 4-33 gives their bit for-
mats
Table 4-34. FIFO Diagnostic Registers
Bit
Name
Description
GX_BASE+8378h-837Bh
31:0
DISPLAY FIFO
DIAGNOSTIC
DATA
GX_BASE+837Ch-837Fh
31:0
COMPRESSED
FIFO DIAGNOS-
TIC DATA
DC_DFIFO_DIAG Register (R/W)
Default Value = xxxxxxxxh
Display FIFO Diagnostic Read or Write Data: Before this register is accessed, the DIAG bit in
DC_GENERAL_CFG register (see Table 4-29 on page 144) should be set high and the DFLE bit
should be set low. Since, each FIFO entry is 64 bits, an even number of write operations should be
performed. Each pair of write operations will cause the FIFO write pointer to increment automati-
cally. After all write operations have been performed, a single read of don't care data should be per-
formed to load data into the output latch. Each subsequent read will contain the appropriate data
which was previously written. Each pair of read operations will cause the FIFO read pointer to incre-
ment automatically. A pause of at least four core clocks should be allowed between subsequent read
operations to allow adequate time for the shift to take place.
DC_CFIFO_DIAG Register (R/W)
Default Value = xxxxxxxxh
Compressed Data FIFO Diagnostic Read or Write Data: Before this register is accessed, the
DIAG bit in DC_GENERAL_CFG (see Table 4-29 on page 144) register should be set high and the
DFLE bit should be set low. Also, the DIAG bit in DC_OUTPUT_CFG (see Table 4-29) should be set
high and the CFRW bit in DC_OUTPUT_CFG should be set low. After each write, the FIFO write
pointer will automatically increment. After all write operations have been performed, the CFRW bit of
DC_OUTPUT_CFG should be set high to enable read addresses to the FIFO and a single read of
don't care data should be performed to load data into the output latch. Each subsequent read will
contain the appropriate data which was previously written. After each read, the FIFO read pointer
will automatically increment.
www.national.com
154
Revision 1.1