GXLV Datasheet, PDF (40/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Signal Definitions (Continued)
2.2.6 Internal Test and Measurement Signals (Continued)
Signal Name
BGA SPGA
Pin No. Pin No.
Type Description
TMS
TEST
H1
(PU)
N3
(PU)
F3
(PD)
J5
(PD)
I
Test Mode Select
JTAG test-mode select.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
I
Test
Test-mode input.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
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