GXLV Datasheet, PDF (161/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.6.2.3 SMI Generation
VGA emulation software is notified of VGA memory
accesses by an SMI generated in dedicated circuitry in
the processor core that detects and traps memory
accesses. The SMI generation hardware for VGA memory
addresses is in the second stage of instruction decoding
on the processor core. This is the earliest stage of instruc-
tion decode where virtual addresses have been translated
to physical addresses. Trapping after the execution stage
is impractical, because memory write buffering will allow
subsequent instructions to execute.
The VGA emulation code requires the SMI to be gener-
ated immediately when a VGA access occurs. The SMI
generation hardware can optionally exclude areas of VGA
memory, based on a 32-bit register which has a control bit
for each 2 KB region of the VGA memory window. The
control bit determines whether or not an SMI interrupt is
generated for the corresponding region. The purpose of
this hardware is to allow the VGA emulation software to
disable SMI interrupts in VGA memory regions that are
not currently displayed.
For direct display modes (8 bpp or 16 bpp) in the display
controller, Virtual VGA can operate without SMI genera-
tion.
The SMI generation circuit on the GXLV processor has
configuration registers to control and mask SMI interrupts
in the VGA memory space.
4.6.2.4 VGA Range Detection
The VGA range detection circuit is similar to the SMI gen-
eration hardware, however, it resides in the internal bus
interface address mapping unit. The purpose of this hard-
ware is to notify the graphics pipeline when accesses to
the VGA memory range A0000h to BFFFFh are detected.
The graphics pipeline has VGA read and write path hard-
ware to process VGA memory accesses. The VGA range
detection can be configured to trap VGA memory
accesses in one or more of the following ranges: A0000h
to AFFFFh (EGA,VGA), B0000h to B7FFFh (MDA), or
B8000h to BFFFFh (CGA).
4.6.2.5 VGA Sequencer
The VGA sequencer is located at the front end of the
graphics pipeline. The purpose of the VGA sequencer is
to divide up multiple-byte read and write operations into a
sequence of single-byte read and write operations. 16-bit
or 32-bit X-bus write operations to VGA memory are
divided into 8-bit write operations and sent to the VGA
write path. 16-bit or 32-bit X-bus read operations from
VGA memory are accumulated from 8-bit read operations
over the VGA read path. The sequencer generates the
lower two bits of the address.
4.6.2.6 VGA Write/Read Path
The VGA write path implements standard VGA write oper-
ations into VGA memory. No SMI is generated for write
path operations when the VGA access is not displayed.
When the VGA access is displayed, an SMI is generated
so that the SMI emulation can update the frame buffer.
The VGA write path converts 8-bit write operations from
the sequencer into 32-bit VGA memory write operations.
The operations performed by the VGA write path include
data rotation, raster operation (ALU), bit masking, plane
select, plane enable, and write modes.
The VGA read path implements standard VGA read oper-
ations from VGA memory. No SMI is needed for read-path
operations. The VGA read path converts 32-bit read oper-
ations from VGA memory to 8-bit data back to the
sequencer. The basic operations performed by the VGA
read path include color compare, plane-read select, and
read modes.
4.6.2.7 VGA Address Generator
The VGA address generator translates VGA memory
addresses up to the address where the VGA memory
resides on the GXLV processor. The VGA address gener-
ator requires the address from the VGA access (A0000h
to BFFFFh), the base of the VGA memory on the GXLV
processor, and various control bits. The control bits are
necessary because addressing is complicated by
odd/even and Chain 4 addressing modes.
4.6.2.8 VGA Memory
The VGA memory requires 256 KB of memory organized
as 64 KB by 32 bits. The VGA memory is implemented as
part of system memory. The GXLV processor partitions
system memory into two areas, normal system memory
and graphics memory. System memory is mapped to the
normal physical address of the DRAM, starting at zero
and ending at memory size. Graphics memory is mapped
into high physical memory, contiguous to the registers and
dedicated cache of the GXLV processor. The graphics
memory includes the frame buffer, compression buffer,
cursor memory, and VGA memory. The VGA memory is
mapped on a 256 KB boundary to simplify the address
generation
Revision 1.1
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