GXLV Datasheet, PDF (66/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Processor Programming (Continued)
3.5.2 Segment Mechanisms
Memory is divided into contiguous regions called “seg-
ments.” The segments allow the partitioning of individual
elements of a program. Each segment provides a zero
address-based private memory for such elements as
code, data, and stack space.
The segment mechanisms select a segment in memory.
Memory is divided into an arbitrary number of segments,
each containing usually much less than the 2³² byte (4
GB) maximum.
There are two segment mechanisms, one for real and vir-
tual 8086 operating modes, and one for protected mode.
3.5.2.1 Real Mode Segment Mechanism
In real mode operation, the CPU addresses only the low-
est 1 MB of memory. In this mode a selector located in
one of the segment registers is used to locate a segment.
To calculate a physical memory address, the 16-bit seg-
ment base address located in the selected segment regis-
ter is multiplied by 16 and then a 16-bit offset address is
added. The resulting 20-bit address is then extended with
twelve zeros in the upper address bits to create a 32-bit
physical address.
The value of the selector (the INDEX field) is multiplied by
16 to produce a base address (see Figure 3-4). The base
address is summed with the instruction offset value to pro-
duce a physical address.
3.5.2.2 Virtual 8086 Mode Segment Mechanism
In virtual 8086 mode the operation is performed as in real
mode except that a paging mechanism is added. When
paging is enabled, the paging mechanism translates the
linear address into a physical address using cached look-
up tables (refer to Section 3.5.4 “Paging Mechanism” on
page 77).
Offset Mechanism
Selected Segment
Register
Offset Address ¹⁶
20
16
20
X 16
Base Address
000h 12 High Order Address Bits
12
32
Linear Address
(Physical Address)
Figure 3-4. Real Mode Address Calculation
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