GXLV Datasheet, PDF (164/247 Pages) National Semiconductor (TI) – Geode™ GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)
4.6.4 Virtual VGA Register Descriptions
This section describes the registers contained in the
graphics pipeline used for VGA emulation. The graphics
pipeline maps 200h locations starting at
GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-
ters” on page 99 for instructions on accessing these regis-
ters.
The registers are summarized in Table 4-38, followed by
detailed bit formats in Table 4-39.
GX_BASE+
Memory Offset
8140h-8143h
8144h-8147h
8210h-8213h
8214h-8217h
Table 4-38. Virtual VGA Register Summary
Type
R/W
R/W
R/W
R/W
Name/Function
GP_VGA_WRITE
Graphics Pipeline VGA Write Patch Control Register: Controls the VGA memory
write path in the graphics pipeline.
GP_VGA_READ
Graphics Pipeline VGA Read Patch Control Register: Controls the VGA memory
read path in the graphics pipeline.
GP_VGA_BASE VGA
Graphics Pipeline VGA Memory Base Address Register: Specifies the offset of
the VGA memory, starting from the base of graphics memory.
GP_VGA_LATCH
Graphics Pipeline VGA Display Latch Register: Provides a memory mapped
way to read or write the VGA display latch.
Default Value
xxxxxxxxh
00000000h
xxxxxxxxh
xxxxxxxxh
www.national.com
164
Revision 1.1