MC68HC908LJ24 Datasheet, PDF (83/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Configuration Registers (CONFIG)
Configuration Register 2 (CONFIG2)
PEE — Port E Enable
Setting PEE configures the PTE0/FP11–PTE7/FP18 pins for LCD
frontplane driver use. Reset clears this bit.
1 = PTE0/FP11–PTE7/FP18 pins configured as LCD frontplane
driver pins: FP11–FP18
0 = PTE0/FP11–PTE7/FP18 pins configured as standard I/O pins:
PTE0–PTE7
STOP_IRCDIS — Internal RC Oscillator Stop Mode Disable
Setting STOP_IRCDIS disables the internal RC oscillator during stop
mode. When this bit is cleared, the internal RC oscillator continues to
operate in stop mode. Reset clears this bit.
1 = Internal RC oscillator disabled during stop mode
0 = Internal RC oscillator enabled during stop mode
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator
to continue operating in stop mode. This is useful for driving the real
time clock module to allow it to generate periodic wake up while in
stop mode. When this bit is cleared, the external XTAL oscillator will
be disabled during stop mode. Reset clears this bit.
1 = XTAL oscillator enabled during stop mode
0 = XTAL oscillator disabled during stop mode
DIV2CLK — Divide-by-2 Clock Bypass
When CGMXCLK is selected to drive the system clocks (BCS=0),
setting DIV2CLK allows the CGMXCLK to bypass the divide-by-2
divider in the CGM module; CGMOUT will equal CGMXCLK and bus
clock will equal CGMXCLK divide-by-2.
DIV2CLK bit has no effect when the BCS=1 in the PLL control
register (CGMVCLK selected and divide-by-2 always enabled). Reset
clears this bit.
1 = Divide-by-2 divider bypassed;
When BSC=0, CGMOUT equals CGMXCLK
0 = Divide-by-2 divider enabled;
When BSC=0, CGMOUT equals CGMXCLK divide-by-2
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Configuration Registers (CONFIG)
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Data Sheet
83