MC68HC908LJ24 Datasheet, PDF (237/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Real Time Clock (RTC)
RTC Registers
12.10.5 RTC Status Register (RTCSR)
The RTC status register contains eight status flags. When a flag is set
and the corresponding interrupt enable bit is also set, a CPU interrupt
request is generated.
Address: $0044
Read: ALMF CHRF DAYF HRF MINF SECF TB1F TB2F
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-10. RTC Status Register (RTCSR)
ALMF — Alarm Flag
This clearable, read-only bit is set when the value in the RTC hour and
minute counters matches the value in the alarm hour and alarm
minute registers. When the ALMIE bit in RTCCR1 is set, ALMF
generates a CPU interrupt request. In normal operation, clear the
ALMF bit by reading RTCSR with ALMF set and then reading the
alarm hour register (ALHR). Reset clears ALMF.
1 = RTC hour and minute counters matches the
alarm hour and minute registers
0 = No matching between hour and minute counters and alarm
hour and minute registers
CHRF — Chronograph Flag
This clearable, read-only bit is set on every tick of the chronograph
counter (every counter count). The tick is on every 1/128 seconds
(see 12.5.4 Chronograph Functions). When the CHRIE bit in
RTCCR1 is set, CHRF generates a CPU interrupt request. In normal
operation, clear the CHRF bit by reading RTCSR with CHRF set and
then reading the chronograph data register (CHRR). Reset clears
CHRF.
1 = A chronograph counter tick has occurred
0 = No chronograph counter tick has occurred
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Real Time Clock (RTC)
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Data Sheet
237