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MC68HC908LJ24 Datasheet, PDF (119/464 Pages) Motorola, Inc – Microcontrollers
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
The relationship between the VCO frequency, fVCLK, and the
reference frequency, fRCLK, is
fVCLK
=
2----P----N---
R
(
fRCL
K
)
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance,
choose fRCLK to a value determined either by other module
requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range
allows. See Section 24. Electrical Specifications. Choose the
reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose fRCLK to
an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this
requirement, use the following equation to solve for R with
practical choices of fRCLK, and choose the fRCLK that gives the
lowest R.
R
=
round
RM
AX
×
⎧
⎨
⎩
⎛
⎜
⎝
f--V----fC--R--L--C-K--L-D--K--E----S- ⎠⎟⎞
–
i
nte
ge
r
⎛
⎜
⎝
-f-V----fC--R--L--C-K--L-D--K--E----S- ⎠⎟⎞
⎫
⎬
⎭
4. Calculate N:
N
=
r
oun
⎛
d⎜
⎝
-R----f-×-R---C-f--V-L---CK---L--×-K----2D---P-E---S--⎠⎟⎞
5. Calculate and verify the adequacy of the VCO and bus
frequencies fVCLK and fBUS.
fVCLK
=
2----P----N---
R
(
fRCL
K
)
fBUS
=
-f-V---C--L---K-
2P × 4
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
119