MC68HC908LJ24 Datasheet, PDF (392/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
18.6.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Write:
Reset: 0
0
0
0
0
0
0
Figure 18-14. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 18-15 shows
the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 18-15. Port D I/O Circuit
Data Sheet
392
MC68HC908LJ24/LK24 — Rev. 2
Input/Output (I/O) Ports
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