MC68HC908LJ24 Datasheet, PDF (423/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Functional Description
The LVI trip point selection bits, LVISEL[1:0], select the trip point
voltage, V_TRIPF, to be configured for 5V or 3V operation. The actual trip
points are shown in Section 24. Electrical Specifications.
Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever
the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0).
NOTE:
After a power-on reset (POR) the LVI’s default mode of operation is 3V.
If a 5V system is used, the user must modified the LVISEL[1:0] bits to
raise the trip point to 5V operation. Note that this must be done after
every power-on reset since the default will revert back to 3V mode after
each power-on reset. If the V_DD supply is below the 3V mode trip voltage
when POR is released, the MCU will immediately go into reset. The LVI
in this case will hold the MCU in reset until either V_DD goes above the
rising 3V trip point, V_TRIPR, which will release reset or V_DD decreases to
approximately 0V which will re-trigger the power-on reset.
LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the
configuration registers. See Section 5. Configuration Registers
(CONFIG) for details of the LVI’s configuration bits. Once an LVI reset
occurs, the MCU remains in reset until V_DD rises above a voltage,
V_TRIPR, which causes the MCU to exit reset. See 9.4.2.5 Low-Voltage
Inhibit (LVI) Reset for details of the interaction between the SIM and the
LVI. The output of the comparator controls the state of the LVIOUT flag
in the LVI status register (LVISR). The LVIIE, LVIIF, and LVIIACK bits in
the LVISR control LVI interrupt functions.
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Low-Voltage Inhibit (LVI)
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Data Sheet
423