MC68HC908LJ24 Datasheet, PDF (239/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Real Time Clock (RTC)
RTC Registers
TB1F — Timebase 1 Flag
This clearable, read-only bit is set on every tick of the timebase 1
counter (every 0.5 or 0.125 seconds). When the TB1IE bit in RTCCR1
is set, TB1F generates a CPU interrupt request. In normal operation,
clear the TB1F bit by reading RTCSR with TB1F set and then reading
the chronograph data register (CHRR). Reset clears TB1F.
1 = A timebase 1 tick has occurred
0 = No timebase 1 tick has occurred
NOTE:
Timebase 1 is not synchronized to the compensated RTC 1-Hz clock.
Hence, time intervals for timebase ticks may not align with the RTC clock
and calendar register updates.
TB2F — Timebase 2 Flag
This clearable, read-only bit is set on every tick of the timebase 2
counter (every 0.25 or 0.0625 seconds). When the TB2IE bit in
RTCCR1 is set, TB2F generates a CPU interrupt request. In normal
operation, clear the TB2F bit by reading RTCSR with TB2F set and
then reading the chronograph register (CHRR). Reset clears TB2F.
1 = A timebase 2 tick has occurred
0 = No timebase 2 tick has occurred
NOTE:
Timebase 2 is not synchronized to the compensated RTC 1-Hz clock.
Hence, time intervals for timebase ticks may not align with the RTC clock
and calendar register updates.
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Real Time Clock (RTC)
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Data Sheet
239