MC68HC908LJ24 Datasheet, PDF (262/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Infrared Serial Communications
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
Slow Data Tolerance
Figure 13-10 shows how much a slow received character can be
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit
data samples at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
MSB
STOP
DATA
SAMPLES
Figure 13-10. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 13-10, the receiver
counts 154 RT cycles at the point when the count of the transmitting
device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
1----5---4-----–_{-----1---4---7-- × 100 = 4.54%}
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 13-10, the receiver
counts 170 RT cycles at the point when the count of the transmitting
device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
Data Sheet
262
MC68HC908LJ24/LK24 — Rev. 2
Infrared Serial Communications Interface Module (IRSCI)
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